(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to processes for forming contact to field effect transistors in CMOS integrated circuits.
(2) Description of Prior Art and Background to the Invention
Complimentary metal oxide semiconductor(CMOS) field effect transistor(FET) technology involves the formation n-channel FETs(NMOS) and p-channel FETs(PMOS) in combination to form low current, high performance integrated circuits. The use of complimentary NMOS and PMOS devices, typically in the form of a basic inverter device, allows a considerable increase of circuit density of circuit elements by reduction of heat generation. The increase in device density accompanied by the shrinkage of device size has resulted in improved circuit performance and reliability as well as reduced cost. For these reasons CMOS integrated circuits have found widespread use, particularly in digital applications.
A number of ion implantation process steps are required to form MOSFET devices and because the PMOS devices require a p-type dopant ion implant where the NMOS devices require an n-type dopant, twice the number of implantation steps are typically required to concurrently form the two device types. The conventional procedure for an implantation operation is to mask the regions of one device type while the corresponding regions of the other type are implanted. The first mask is then stripped and another mask is applied over the just implanted devices while the devices of the first type receive the implantation.
The photoresist masks used to protect devices of one type while devices of the other type are implanted are often referred to as "block out" masks. They may be distinguished from other photoresist masks used in integrated circuit processing by the fact that they do not require as precise an alignment procedure as the other masks. Block out masks are also used to mask features of one type device while processing the other type. Hsu, et.al., U.S. Pat. No. 5,460,993 apply a block out mask to NMOS device sidewalls while PMOS device sidewalls are etched to make them narrower.
In a prior art process for forming contacts to the elements of CMOS semiconductive devices, an interlevel dielectric(ILD) layer is deposited over the devices. The ILD layer is first planarized and then a photoresist layer is applied. Contact openings are patterned in a photoresist layer for both the PMOS and NMOS devices.
Openings are formed in the ILD layer by anisotropic etching. After the contact openings are formed, the exposed conductive material at the base of the contact openings is provided with a supplemental ion implant prior to the deposition of contact material, for example tungsten plugs, The supplemental ion implant is required to reinforce the dopant concentration of the silicon at the base of the contact openings in order to assure a reliable low resistance ohmic contact. This is done by means of a shallow ion implant into the contact openings. Since both n- and p-type contacts in the CMOS integrated circuit have been opened by the contact etch, it is necessary to apply a block out photoresist mask to cover the p-contact openings while the n-contacts are implanted. After the n-contact implant, the p-contact block out mask is stripped and an n-contact block out mask is applied and patterned to protect the n-contacts during the p-contact ion implant. The overall process sequence requires three photolithographic steps entailing an all-contact mask and two block out masks. The sequence of steps in the prior art process are shown on the left side of FIG. 6. The three photo steps are marked with an asterisk.
One of the most handling intensive and complex processing procedures in integrated circuit manufacturing is photolithographic patterning. This procedure involves a great deal of wafer manipulation and exposure of wafers to environments which subject them to particulate contamination. A photoresist coating is first applied by spinning the wafer on a chuck and delivering the liquid photoresist through a nozzle. The photoresist film is then cured by baking, often by a several treatments at different temperatures. Next the wafer is mounted in an exposure apparatus, typically a stepper, and is mechanically stepped under a system of optics whereby each integrated circuit die is exposed to a reticle pattern. Finally, the wafer is passed though a sequence of photo development solutions to develop the mask image. Because of the great impact of photolithography on product yield. It is a goal of the process designer to necessitate as few photolithographic steps as possible.
A method of modifying a process to reduce the number of photomask steps is illustrated by Dennison, U.S. Pat. No. 5,292,677 wherein a combination of an etch stop layer and a critical partial etch permits the definition of three essentially different contacts by a single photomask step.